An integrated circuit or circuit assembly generally contains one or more clocks, either generated internally or controlled externally. Each clock is distributed to a set of storage cells via a skew-minimized network, which delivers a clock pulse to all the storage cells at virtually the same time. Such a clock, its related storage cells and all combinational logic blocks bounded by the storage cells, form a clock domain.
Scan testing of circuits is well known and is the most widely used design-for-test (DFT) technique used to test integrated circuits. It replaces all or part of original storage cells with scan cells that may be linked to form one or more scan chains. A scan-based integrated circuit or circuit assembly can be tested by repeating a shift cycle followed by a capture cycle. In a shift cycle, pseudorandom or predetermined test stimuli are shifted into all scan chains, making their outputs as controllable as primary inputs. In a capture cycle, test responses are latched into some or all scan chains, making their inputs as observable as primary outputs, because the values captured into scan chains can be shifted out in the next shift cycle.
Scan based tests are expensive because of the high capital investment in test equipment and because they can require a considerable amount of time to run. Test times for scan based tests depend on how fast the test is being run and the volume of the test, e.g., the magnitude of the test pattern. Due to high demands to reduce test costs of scan based tests and optimize turn-around time for integrated circuit releases, scan operations need to be run at increasingly higher clock speeds.
Running scan operations at higher clock speeds helps in reducing the overall test time. However, it can cause power issues resulting in flip-flops and gates behaving incorrectly under inadequate power supply conditions. This could cause false failures due to the electrical and thermal stressing of the silicon under test, which could result in significant yield loss. Accordingly, users of the test system are left with no other alternative but to slow down the clock speeds in order to minimize power related issues, which results in longer test times.
Further, the dynamic power consumption during scan test, with and without test compression, is always higher than the functional mode because of very high toggling rates and logic activity during scan shift and scan capture operations and can result in excessive heat dissipation during testing that can damage the package. This increased dynamic power consumption can cause reliability issues in chips, which may result in the chip subsequently failing in the field. This is because during scan test mode, power dissipation will exceed the peak power for which the chip and package has been designed.
Certain conventional systems have attempted to address power reduction during scan capture cycles, but they are either costly in terms of computation time or require significant implementation and verification efforts. For example, certain techniques have been developed in the industry to perform low power ATPG pattern generation where, based on a predetermined toggle estimate, pattern generation tools will enable clock gating cells for certain regions of the integrated circuit while disabling others. However, this technique requires considerable memory and CPU resources.
Further, low power capture X-filling methods in ATPG have also been developed to reduce the number of transitions at the output of scan flip-flops in capture mode. However, these methods also are problematic because they lead to lower defect coverage than random-fill.
Additionally, other conventional systems implement low power capture logic such that based on a given target, the ATPG tool can be enabled to capture clock activity in selective regions of the integrated circuit. An example of the technique is disclosed in U.S. patent application Ser. Nos. 13/444,780 and 13/444,782, both entitled “Power Droop Reduction Via Clock-Gating For At-Speed Scan Testing” and naming Amit Sanghani and Bo Yang as inventors. This technique is efficient because it prevents the ATPG tool from performing too many computations, and it is faster in terms of run time, however, significant implementation and verification efforts are required to implement it and there is considerable logic overhead.